`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:13:13 10/24/2012 
// Design Name: 
// Module Name:    MEM_CTR 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MEM_WR #(parameter LOG_DEPTH=8, DEPTH=256, WIDTH=16)
(
	
	 input clk,
	 input rst,
	 input signed [WIDTH-1:0] in_r,
	 input signed [WIDTH-1:0] in_i,
    output reg signed[WIDTH-1:0] out_r,
    output reg signed[WIDTH-1:0] out_i,
	 output reg[LOG_DEPTH-1:0] addr,
	 output reg wr_en
	 
    );

	always@(posedge clk or negedge rst)
	if(!rst)	
	begin
		out_r <= 0;
		out_i <= 0;
	end
	else
	begin
		out_r <= in_r;
		out_i <= in_i;
	end
	
	
	always@(posedge clk or negedge rst)
	if(!rst)
		addr <= 0;
	else if(addr == DEPTH-1)
		addr <= 0;
	else
		addr <= addr + 1;
	
	
	always@(posedge clk or negedge rst)
	if(!rst)
		wr_en <= 1'b0;
	else
		wr_en <= 1'b1;
	
	
endmodule
